1. Field of the Invention
The present invention relates to a semiconductor device and fabrication process. More particularly, the present invention relates to a method of fabricating spacers and its post-etching cleaning and semiconductor device.
2. Description of the Related Art
In the conventional method of fabricating a metal oxide semiconductor (MOS) transistor, spacers are often formed on the respective sidewalls of the gate to increase the degree of isolation between the source/drain regions and the gate. More importantly, the entire structure including the spacers and the gate can be utilized to form the source/drain regions in a doping step.
In general, the process of fabricating the gate spacers includes sequentially forming a gate oxide layer and a polysilicon layer over a semiconductor substrate. Then, the gate oxide layer and the polysilicon layer are defined to form a gate structure. Thereafter, a silicon nitride layer is formed to cover the entire gate structure. After that, an etching process is performed to form silicon nitride spacers on the respective sidewalls of the gate structure. After performing the spacer etching process and before carrying out a subsequent process, the entire wafer will be immersed in a rinsing tank to perform a cleaning step so that any micro particles and post-etching residual polymer attached to the substrate are removed.
However, the chemical cleaning solution in the rinsing operation frequently leads to some damages to the surface of the spacers and the attrition of the spacer film layer resulting in a reduction of the width of the spacers. Ultimately, the short channel effect will be amplified and gate-source/drain capacitance value will be increased. Furthermore, the cleaning step also leads to a slight problem in controlling the width of the spacers.